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HI-5701/883
June 1994
6-Bit, 30 MSPS Flash A/D Converter
Description
The HI-5701/883 is a monolithic, 6-bit, CMOS Flash Analogto-Digital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 30 MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5701/ 883 delivers 0.7 LSB differential nonlinearity while consuming only 250mW (typical) at 30 MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 7-bit resolution.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 30 MSPS with No Missing Codes * 20MHz Full Power Input Bandwidth * No Missing Codes Over Temperature * Sample and Hold Not Required * Single +5V Supply Voltage * CMOS/TTL * Overflow Bit
Applications
* Video Digitizing * Radar Systems * Medical Imaging * Communication Systems * High Speed Data Acquisition Systems
Ordering Information
PART NUMBER HI1-5701T/883 TEMPERATURE RANGE -55oC to +125oC PACKAGE 18 Lead CerDIP
Pinout
HI-5701/883 (18 LEAD CERDIP) TOP VIEW
D5 (MSB) 1 OVF 2 VSS 3 18 D4 17 D3 16 1/2R 15 D2 14 D1 13 D0 (LSB) 12 VDD 11 VIN 10 VREF -
Functional Block Diagram
1 2 VIN 11 VREF + 9 1 1 2
D CL Q
R/2
COMP 64
OVERFLOW 2 (OVF) 1 D5 (MSB) 3 D4
R
D CL Q
R R R R
D CL Q
NC 4 CE2 5 CE1 6 CLK 7 PHASE 8 VREF + 9
COMPARATOR LATCHES AND ENCODER LOGIC
COMP 63
1/2R 16
D CL Q
4 D3 5 D2 10 D1 11 D0 (LSB) 16 CE1 15 CE2
COMP 32
D CL Q
D CL Q
R VREF - 10 R/2
COMP 2
D CL Q
COMP 1
VDD 12 CLK PHASE 7 8 2 (SAMPLE) 1 (AUTO BALANCE) VSS 3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number
6-14
512031 File Number 3378
HI-5701/883 Pin Description
PIN # 1 2 3 4 5 6 7 8 NAME D5 OVF VSS NC CE2 CE1 CLK PHASE Bit 6, Output (MSB) Overflow, Output Digital Ground No Connection Three-State Output Enable Input, Active high (See Truth Table) Three-State Output Enable Input, Active Low (See Truth Table) Clock Input Sample Clock Phase Control Input. When Phase is Low, Sample Unknown (1) occurs when the Clock is Low and Auto Balance (2) occurs when the Clock is High (See Phase Control Table) Reference Voltage Positive Input Reference Voltage Negative Input Analog Signal Input Power Supply, +5V Bit 1, Output (LSB) Bit 2, Output Bit 3, Output Reference Ladder Midpoint Bit 4, Output Bit 5, Output DESCRIPTION
9 10 11 12 13 14 15 16 17 18
VREF + VREF VIN VDD D0 D1 D2 1/2R D3 D4
Chip Enable Truth Table
CE1 0 1 X X = Don't Care. CE2 1 1 0 D0 - D5 Valid Three-State Three-State Valid Valid Three-State OVF
Phase Control
CLOCK 0 0 1 1 PHASE 0 1 0 1 INTERNAL GENERATION Sample Unknown (2) Auto Balance (1) Auto Balance (1) Sample Unknown (2)
Spec Number 6-15
512031
Specifications HI-5701/883
Absolute Maximum Ratings
Supply Voltage, VDD to VSS . . . . . . . . . . . (VSS - 0.5) < VDD < +7.0V Analog and Reference Input Pins. .(VSS - 0.5) < VINA < (VDD +0.5V) Digital I/O Pins . . . . . . . . . . . . . . . . (VSS - 0.5) < VI/O < (VDD +0.5V) Operating Temperature Range HI1-5701T/883 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Storage Temperature Range . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300oC ESD Clasification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . 700C/W 28oC/W Power Dissipation at +75oC (Note 1) HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4mW Power Dissipation Derating Factor Above +75oC HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14mW/oC Reliability Information Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4815 Worst Case Density . . . . . . . . . . . . . . . . . . . . . . . . 3.05 x 104A/cm2
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETERS ACCURACY Integral Linearity Error (Best Fit Method) INL FS = 20MHz, fIN = DC 1 2, 3 FS = 30MHz, fIN = DC 1 2, 3 Differential Linearity Error (Guaranteed No Missing Codes) DNL FS = 20MHz, fIN = DC 1 2, 3 FS = 30MHz, fIN = DC 1 2, 3 Offset Error (Adjustable to Zero) VOS FS = 20MHz, fIN = DC 1 2, 3 Full Scale Error (Adjustable to Zero) FSE FS = 20MHz, fIN = DC 1 2, 3 ANALOG INPUT Analog Input Resistance RIN VIN = 4V 1 2, 3 Analog Input Bias Current IB VIN = 0V, 4V 1 2, 3 REFERENCE INPUT Total Reference Resistance RL 1 2, 3 +25oC +125oC, -55oC 250 235 +25oC +125oC, -55oC +25oC +125oC, -55oC 4 4 1.0 1.0 M M A A +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC SYMBOL CONDITIONS GROUP A SUBGROUP TEMPERATURE MIN MAX UNIT
1.25 2.0 1.5 2.5 0.6 0.75 0.75 1.0 2.0 2.5 2.0 2.5
LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB
Spec Number 6-16
512031
Specifications HI-5701/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETERS DIGITAL INPUTS Input High Voltage VIH 1 2, 3 Input Low Voltage VIL 1 2, 3 Logic Input Current IIN VIN = 0V, +5V 1 2, 3 DIGITAL OUTPUTS Output Leakage IOZ CE2 = 0V, VO = 0V, 5V 1 2, 3 Output Logic Source Current IOH VO = 4.5V 1 2, 3 Output Logic Sink Current IOL VO = 0.4V 1 2, 3 POWER SUPPLY REJECTION Offset Error PSRR VOS VDD = 5V 10% 1 2, 3 Gain Error PSRR FSE VDD = 5V 10% 1 2, 3 POWER SUPPLY CURRENT Supply Current IDD FS = 30MHz 1 2, 3 NOTE: 1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. +25oC +125oC, -55oC 60 75 mA mA +25oC +125oC, -55oC +25oC +125oC, -55oC 1.0 1.5 1.0 1.5 LSB LSB LSB LSB +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC -3.2 -3.2 3.2 3.2 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC 2.0 2.0 0.8 0.8 V V V V A A SYMBOL CONDITIONS GROUP A SUBGROUP TEMPERATURE MIN MAX UNIT
1 1
1.0 1.0
-
A A mA mA mA mA
Spec Number 6-17
512031
Specifications HI-5701/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETER Maximum Conversion Rate SYMBOL CONDITIONS No Missing Codes GROUP A SUBGROUP 9 10, 11 Data Output Enable Time tEN 9 10, 11 Data Output Disable Time tDIS 9 10, 11 Data Output Delay tOD 9 10, 11 Data Output Hold tH 9 10, 11 TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 30 30 10 5 MAX 20 20 20 20 20 20 UNIT MSPS MSPS ns ns ns ns ns ns ns ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) Device Characterized at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETER Minimum Conversion Rate NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. SYMBOL CONDITIONS No Missing Codes TEMPERATURE +25oC, +125oC, -55oC MIN MAX 0.125 UNIT MSPS
TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA. SUBGROUPS (SEE TABLES 1 AND 2) 1 1 (Note 1), 2, 3, 9, 10, 11 1, 2, 3, 9, 10, 11 1
Spec Number 6-18
512031
HI-5701/883 Die Characteristics
DIE DIMENSIONS: 2220m x 3320m x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA DIE ATTACH: Material: Gold Silicon Eutectic Alloy Temperature: Ceramic DIP - 460oC (Max) WORST CASE CURRENT DENSITY: 3.05 x 104 A/cm2
Metallization Mask Layout
HI-5701/883
OVF
VSS
D5
D4
VSS
D3
1/2R
D2
CE2
D1
D0
CE1
VDD
PHASE
CLK
VIN
VREF +
VREF -
VDD
Spec Number 6-19
512031
HI-5701/883 Timing Waveforms
CLOCK INPUT PHASE - HIGH COMPARATOR DATA IS LATCHED 2 1 2 1 2 1 2 1 ENCODED DATA IS LATCHED INTO THE OUTPUT REGISTERS 2
CLOCK INPUT PHASE - LOW
SAMPLE N-2
AUTO BALANCE tAB
SAMPLE N-1
AUTO BALANCE
SAMPLE N
AUTO BALANCE
SAMPLE N+1
AUTO BALANCE
SAMPLE N+2
ANALOG INPUT
tAP tH tAJ tOD
DATA OUTPUT
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1 CE2 tEN tDIS
tDIS D0 - D5 HIGH
tEN
DATA
DATA
HIGH IMPEDANCE
DATA
IMPEDANCE
OVF
DATA
HIGH IMPEDANCE
DATA
FIGURE 2. OUTPUT ENABLE TIMING
Burn-In Circuit
HI-5701/883 CerDIP
+5V 1 CAP 0V C1 0.01F/0.1F 2 3 4 5 6 CLK 7 8 +4V CAP 0V C7 0.01F/0.1F 9 18 17 16 15 14 13 12 11 10 VIN
NOTES: 1. 2. 3. 4. Power supply and the reference voltage input to be decoupled by 0.01F in parallel with 1F capacitor Clock input is a pulse with 1:10 duty cycle, approximately 100KHz and 0V to 4V amplitude VIN, analog input is a slow triangular waveform (FIN = 10KHz) and 0V to 4V amplitude All supplies to be protected with <7V zener diodes
Spec Number 6-20
512031
HI-5701/883 Packaging
FRIT SEAL DUAL-IN-LINE CERAMIC PACKAGE
c1
-A-DBASE METAL E b1 M -BM (b) DS SECTION A-A LEAD FINISH
F18.3 MIL-STD-1835 GDIP1-T18 (D-6, CONFIGURATION A) 18 LEAD FRIT SEAL DUAL-IN-LINE CERAMIC PACKAGE
INCHES SYMBOL
(c)
MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 24.38 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 18 5.08 1.78 105o 0.38 0.76 0.25 0.038 2 8 NOTES 2 3 4 2 3 5 5 6 7
MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220
MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.960 0.310
A b b1 b2 b3 c c1
bbb S
C A-B S D
BASE PLANE -CSEATING PLANE S1 b2 b
Q A L AA
D
eA
E e eA eA/2 L Q S1 S2
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 18 0.200 0.070 105o 0.015 0.030 0.010 0.0015
e
eA/2
c
ccc M C A - B S D S
aaa M C A - B S D S
aaa bbb
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1.
ccc M N
5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling Dimension: Inch.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 727-9207 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 6-21
512031

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